PhD (Low Power VLSI Devices, 2020), National Institute of Technology (NIT), Kurukshetra, India
M.Tech. (Microelectronics and VLSI Design, 2016), Electronic Science Department, Kurukshetra University, India
B.Tech. (Electronics and Communication engineering, 2014), Kurukshetra University, India
Low Power VLSI Design, Semiconductor Device Design and Modelling, Ferroelectric Memory Devices
Assistant Professor, SCNS, JNU, New Delhi (May 2023 – Till Date)
Assistant Professor, NIT Delhi (Jan 2022 – April 2023)
Assistant Professor, PEC Chandigarh (Sept 2021 – Dec 2021)
Assistant Professor, NIT Jalandhar (Jan 2021 – June 2021)
Qualified UGC NET (Electronic Science) 2020
SERB DST Travel Grant (Los Angeles, USA) 2019
- Billel Smaani, Neha Paras, Shiromani Balmukund Rahi, Young Suh Song, Ramakant Yadav, and Subham Tayal, “Impact of the Self-Heating Effect on the Nanosheet FET Performance” ECS Journal of Solid State Science and Technology, Vol. 12, 021005, PP: 1-18, (2023), IOP Science. (ISSN:2162-8777) (DOI: 10.1149/2162-8777/acb96b), Scopus, IF: 2.07, HI: 56.
- Jeetendra Singh, Shailendra Singh and Neha Paras, “Design and Integration of Vertical TFET and Memristor for Better Realization of Logical Functions,” Silicon, Vol. 14, (2022) Springer. (ISSN: 1876-9918). (DOI: 10.1007/s12633-022-02047-1) SCI, Scopus, IF: 2.941, HI: 34.
- Deepika, Neha Paras, Anil Arya, Rajesh Kumar, Shashi Sharma, Sohan Lal, V. Kumar and Anurag Gaur, “Room temperature magento-electric coupling in Pb-Zn substituted Co2Y-hexaferrite,” Journal of Materials Science: Materials in Electronics, Vol. 33, No. 18, (2022), Springer. (ISSN: 0957-4522) (DOI: 10.1007/s10854-022-08561-7) SCI, Scopus, IF: 2.478, HI: 80.
- Neha Paras and S. S. Chauhan, “Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs,” Applied Physics A: Materials Science & Processing, Vol. 125, No. 5, 317, (2019), Springer. (ISSN: 1432-0630). (DOI: 10.1007/s00339-019-2621-x), SCI, Scopus, IF: 2.983, HI: 149
- Neha Paras and S. S. Chauhan, “A novel vertical tunneling based Ge-source TFET with enhanced DC and RF characteristics for prospect low power applications,” Microelectronic Engineering, Vol. 217, 111103, (2019), Elsevier. (ISSN: 0167-9317) (DOI: 10.1016/j.mee.2019.111103), SCI, Scopus, IF: 2.662, HI: 99
- Neha Paras and S. S. Chauhan, “Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications,” Microelectronic Engineering, Vol. 216, 111043, (2019), Elsevier. (ISSN: 0167-9317) (DOI: 10.1016/j.mee.2019.111043), SCI, Scopus, IF: 2.662, HI: 99
- Neha Paras and S. S. Chauhan, “Vertical Tunneling Based Tunnel Field Effect Transistor with Workfunction Engineered Hetero-Gate to Enhance DC Characteristics,” Journal of Nanoelectronics and Optoelectronics, Vol. 14, No.1, (2019), American Scientific Publishers.(ISSN: 1555-1318) (DOI: 10.1166/jno.2019.2427), SCI-E, IF: 1.069, HI: 23